Intel calls its Kentsfield chip a quad-core processor, and it is, in the sense that four cores execute inside one package you plug into one socket. What Intel does not advertise on the box is that the four cores are actually two separate dual-core dies sitting next to each other under the same heat spreader, talking to each other through the same shared front-side bus they would use to talk to anything else on the motherboard.

That is not a flaw exactly. Intel had a working, mature dual-core design and a manufacturing process that could stamp it out cheaply, and gluing two of them together shipped a quad-core desktop chip nearly a year before anyone else had one. The engineering is unglamorous and the performance is real.

AMD is doing something harder. Barcelona, due later this year, is a native quad-core: one die, four cores, a shared L3 cache, an integrated memory controller talking directly to RAM instead of routing through a separate chipset. On paper it is the more elegant design, and AMD has spent a fair amount of the last six months making sure everyone knows it.

The trouble is paper does not ship products, and AMD is behind Intel on the thing that actually determines whether an elegant design turns into a fast chip: the manufacturing process underneath it. Intel is already deep into 65 nanometer with 45 nanometer parts sampling for a launch later this year. AMD is still working through its own transition, and every process generation Intel gets to first is a generation where Intel can run the same design at a higher clock or a lower voltage while AMD cannot.

I do not think Intel’s approach is the better one long term. Two dies on a shared bus does not scale the way a single die with an on-die memory controller does, and Intel knows it, which is why the roadmap eventually points toward doing this properly instead of doing it fast. But “eventually” is doing a lot of work in that sentence, and right now Intel is shipping a compromise that outperforms AMD’s clean design that is not out yet.

Barcelona needs to be genuinely better when it lands in the fall, not just architecturally purer. A more elegant chip that loses on clock speed because it is stuck a process node behind is still a loss.