The Milliwatt War: Where Edge AI Actually Gets Interesting

A typical microcontroller gives you half a megabyte of SRAM and a couple of megabytes of flash to run a neural network on, often under a tenth of a watt, which is something like four orders of magnitude tighter than what a Jetson Thor plays with. This layer interests me more than the humanoid-robot silicon everyone writes about, because this is where the volume lives. The headline parts ship in the thousands; microcontrollers running inference at milliwatts will ship in the billions, inside motors and door locks and water meters nobody will ever call AI, and the companies fighting over that floor are Renesas, Microchip, and Ceva.

Compute stopped being the binding constraint here a while ago. The weights have to physically fit within a few hundred kilobytes, and that one fact shapes every architecture in the space, which is why the cleverest engineering I’ve seen lately goes by the deeply unsexy name NetSqueeze.

Ceva licenses IP rather than selling chips, so its NeuPro line ends up embedded in other people’s silicon. The big accelerator, NeuPro-M, handles generative workloads at the endpoint and shows up in Renesas R-Car parts. The one that matters for the milliwatt war is the NeuPro-Nano, and the architecture is the point: most MCU vendors do AI by taking a stock Arm Cortex-M and bolting on a separate accelerator, usually Arm’s own Ethos, which was the first real microNPU. Ceva went the other way, building the NeuPro-Nano as a single standalone core that runs control code, DSP feature extraction, and the neural-network math in one place, managing its own memory and code loading, so there’s no second core and no shuffling data across a bus, which is exactly the movement that burns power you don’t have.

NetSqueeze is what makes that fit the memory budget. It feeds compressed model weights straight into the engine without a decompression step, which Ceva says reduces the footprint by up to 80%. A dual-core accelerator setup often has to decompress weights into memory, then recompress and feed them to the NPU, paying for the memory twice and burning cycles on the round trip; processing the compressed weights directly kills that whole dance. When your entire SRAM budget runs to a few hundred kilobytes, an 80% cut isn’t a tuning win; it decides whether the model exists at all. Ceva wraps it in a studio SDK that talks to LiteRT for Microcontrollers and µTVM, because nobody is hand-coding these in assembly.

Renesas bought its way in, and it worked. The Reality AI acquisition in July 2023 got them less a chip than a way of thinking about non-visual sensing: point Reality AI Tools at raw vibration or current or sound data, and it finds the right sensor combination and generates a model optimized for an Arm Cortex-M, A, or R core. The use case that sold me is sensorless predictive maintenance, where Renesas pairs the RA6T2 motor-control kit with Reality AI so the inference runs in the motor-control firmware and catches a failing bearing from the motor’s own electrical signature, no extra vibration sensor, almost nothing added to the bill of materials. That last bit is the whole game in industrial. Nobody wants to add a sensor, a wire, and a connector to a million units; inferring the fault from data the controller already has is how this deploys at scale.

Renesas also leaned into explainability, and I wish more of the field would. Reality AI’s models express themselves in time and frequency terms an engineer can inspect, and on a factory line or in a car an unexplainable model that flags a fault you can’t trace isn’t just annoying, it’s a liability. That differentiator gets undersold.

Microchip is the one I find least distinctive, which isn’t the same as losing. Its MPLAB machine-learning tooling gets models onto its PIC, AVR, and Arm parts, and its actual edge is what it has always been, an enormous installed base and a sales reach into every embedded shop on earth. Microchip doesn’t need the cleverest NPU. It needs TinyML to be a checkbox on parts customers already design in, and for a big slice of the market, that’s enough. The boring incumbent move is sometimes the right one.

The model-development tooling these MCU vendors lean on increasingly runs through platforms that got acquired, Edge Impulse most of all, and I followed that thread in the Qualcomm full-stack piece. The milliwatt layer is the bottom floor of the same structure I sketched in the broader evolution, and whoever owns the tooling that targets it has leverage over everyone selling the silicon underneath.

I’m leaving the analog-compute and neuromorphic startups out on purpose, the Mythics and the in-memory crowd, because they chase a different power-performance point and deserve more than a dismissive line. For conventional MCUs here and now, Ceva has the architecture I find most interesting, and Renesas has the industrial story I trust most, but if I had to put money on who wins the decade, I’d bet on Microchip’s distribution, which is a deeply unromantic answer for the part of edge AI I find most romantic. Billions of units were shipped because they were already in the catalog, not because the NPU was elegant.