Intel’s EMIB Finds Its Moment: How a Packaging Bottleneck Is Redrawing the AI Chip Supply Chain

NVIDIA has locked up more than half of TSMC’s CoWoS advanced packaging capacity through 2026 and 2027. That single fact turned a manufacturing step most people never think about into one of the ugliest chokepoints in AI infrastructure, with hyperscalers and custom ASIC teams left fighting over the scraps. Intel walked into that gap with its Embedded Multi-die Interconnect Bridge, and Google reportedly picking EMIB for its ninth-generation TPU is the kind of validation that flips a technology from “credible alternative” to something TSMC actually has to worry about.

TSMC’s CoWoS family (Chip on Wafer on Substrate) comes in three flavors: CoWoS-S with a full silicon interposer, CoWoS-R with a redistribution layer, and CoWoS-L with local silicon bridges. All of them get high-bandwidth die-to-die interconnect the same way, by placing chiplets on a large interposer before mounting the assembly onto a package substrate. The silicon interposer in CoWoS-S can span multiple reticle fields, which buys dense interconnect across a wide area. It costs you in dollars per package, in warpage risk on those big interposer panels, and right now the part that actually hurts, capacity at TSMC’s advanced packaging fabs.

Intel skips the big interposer entirely. Rather than one slab spanning the whole package, EMIB drops small silicon bridge dies into the organic substrate exactly where the high-bandwidth connections need to go and nowhere else. Each bridge is a few millimeters across, packed with dense interconnect wiring, and it hits bandwidth densities that compete with silicon-interposer approaches without dragging a giant interposer along. The organic substrate handles everything else, so material cost per package drops, warpage eases (organic is more mechanically forgiving than a large silicon tile), and package size can grow past the reticle limits that box in monolithic interposers.

This is not a science project. Intel has been shipping EMIB since Kaby Lake-G in 2018, where it stitched an Intel CPU die to an AMD GPU and HBM2 memory, and the current generation has split into specialized variants. EMIB-M bakes silicon capacitors (SiCap) into the package for cleaner power delivery, which matters more than it sounds when AI accelerators push power densities that overwhelm conventional package-level decoupling. EMIB-T adds Through-Silicon Vias to the bridge dies for vertical connectivity on top of the lateral interconnect, and EMIB-T is the variant Google reportedly picked.

Cost is only half the argument. Current EMIB-M supports roughly 6× reticle scaling, meaning the effective package area can be about six times a single lithography exposure field. Intel’s roadmap targets 8 to 12× by 2027 and dangles 40× further out. TSMC’s largest CoWoS packages are also pushing multi-reticle scales, so this is a real fight on scalability, not Intel selling a budget option and hoping nobody notices the ceiling.

Yield is where the numbers get slippery. Intel has cited figures as high as 98% in some announcements, while supply chain sources tracking actual production land closer to 90%. Both are commercially fine, and 90% on a packaging step is respectable, but the gap between 90% and 98% turns into serious money at the volumes Google is reportedly chasing.

Those volumes are the reason anyone is paying attention. The win is Google’s next-generation TPU, codenamed “Humufish” and described as the TPU v8e or ninth-generation part. SemiAnalysis surfaced the EMIB-T selection publicly, tracing sourcing back to Taiwan’s Commercial Times in late April 2025, and the scale being floated is roughly 3 million TPUs packaged via EMIB by 2028.

Google is not buying from Intel directly, which is where it gets interesting. Google designs the TPU, MediaTek handles chip design integration and sits in the middle as the intermediary customer for Intel’s packaging, and Intel supplies the EMIB-T packaging itself. MediaTek COO David Ku confirmed on an earnings call that a data center client had chosen Intel EMIB for a customized AI accelerator, and analysts lined up behind the obvious read that this is the Google program. MediaTek is running CoWoS-based packaging for other projects at the same time, deliberately playing packaging-agnostic: a custom ASIC house that routes any given design through whichever packaging technology best fits the customer on cost, performance, and availability.

That middleman structure is also Intel’s exposure. Reports have Google exploring whether it can hand designs straight to TSMC and cut MediaTek out as a cost-reduction move. Do that for some or all of the Humufish volume and it dents both MediaTek’s role and Intel’s packaging revenue in one stroke. Nothing is confirmed, orders aren’t public, and the whole thing is still fluid heading into the H2 2027 production window Humufish is targeting.

Two more Taiwanese names showed up in the reported supply chain in mid-2025, and one of them is a genuine worry. Powerchip Semiconductor (PSMC), a foundry, is in discussions to expand SiCap production for the EMIB-based TPU. The worry is AP Memory Technology Corp, the IC designer supplying the silicon capacitors that EMIB-M and EMIB-T lean on for power delivery, whose SiCap output is projected at just 10,000 units by end of 2027. Set that against 3 million packaged TPUs and the arithmetic gets uncomfortable. Executives from both companies have reportedly met Intel CEO Lip-Bu Tan. If EMIB demand outruns SiCap supply, Intel solves the CoWoS bottleneck and immediately manufactures a new one in a component nobody’s watching.

TSMC is not sitting still. The company has announced a 60%-plus CoWoS capacity expansion by 2027, and CoWoS-L, which uses local silicon bridges instead of a full interposer, is a direct architectural answer to the advantages EMIB claims. Capacity expansion takes time, though, equipment lead times are long, and the customers already qualifying EMIB won’t walk away from that investment the second TSMC adds fab space. Advanced packaging qualification at hyperscaler volumes runs 12 to 24 months, and once Google validates EMIB-T at scale, that validation lives on as institutional knowledge and supply chain infrastructure whether or not the CoWoS shortage ever eases.

SK Hynix is evaluating EMIB for HBM integration, and that one compounds. HBM sits in virtually every high-end AI accelerator, so if SK Hynix blesses EMIB as a viable HBM integration path, the next customer designing an HBM-equipped AI chip inherits that validation instead of starting cold. Each major validation lowers the barrier for whoever comes next, which is how a packaging ecosystem builds gravity. Meta reportedly evaluating EMIB for its MTIA accelerators would push this from a Google story to a two-hyperscaler platform, signaling that EMIB isn’t a Google-specific workaround.

All of this lands on Intel Foundry, which badly needs a win it can actually bank. The leading-edge node business built around 18A is still trying to convince external customers, with Panasonic named as an early adopter, and the foundry division posted substantial losses through 2024. Packaging revenue is a different animal: it doesn’t ask customers to trust Intel’s logic process, only its packaging, which has a longer track record and harder yield data behind it. Intel placed a major equipment order for EMIB expansion in May 2025 with deliveries expected in late 2026, spanning facilities in the United States and Vietnam. That is a multi-year capital commitment, and the timing is not an accident: gear arriving in late 2026 lines Intel up to ramp EMIB capacity right as the Humufish window opens in H2 2027.

The bigger prize is the combined pitch, leading-edge logic on 18A plus EMIB packaging under one roof, a vertically integrated escape hatch from the TSMC-centric supply chain. That still lives in the conditional tense, because 18A hasn’t shown the external traction it would need to threaten TSMC at scale, but packaging gives Intel a real commercial foothold and cash flow while the logic side either grows up or doesn’t.

Advanced packaging for AI-grade silicon is a multi-billion dollar segment, and TSMC owns something close to a monopoly in the top tier. That’s comfortable for TSMC and miserable for its customers, who have almost no leverage when there’s no alternative to point at. Google’s reported EMIB adoption at 3 million units is big enough to start moving that needle. Hyperscalers with volume committed to Intel walk into TSMC negotiations with something behind them, and TSMC, fully aware of this, has every reason to loosen up on pricing and allocation for customers who’ve proven they can send volume elsewhere.

Broadcom is the incumbent staring straight down the barrel of the MediaTek-Intel axis. It built a dominant custom-silicon franchise on hyperscaler business, Google’s TPU v4 and v5, Meta’s MTIA, all of it running through Broadcom’s custom ASIC capabilities. MediaTek showing up as a packaging-agnostic ASIC integrator that routes Google’s TPU through Intel EMIB is a direct shot at that model, and Broadcom’s stock has already twitched on reporting about the supply chain shuffle.

None of this means EMIB steamrolls CoWoS. NVIDIA’s H- and B-series GPUs, with their enormous HBM stacks and brutal interconnect demands, are staying on CoWoS for the foreseeable future, because TSMC’s packaging is welded into NVIDIA’s design and supply chain and the performance at that tier is proven. What EMIB is actually eating is the tier just below: AI ASICs, custom accelerators, and mid-range AI silicon where cost, availability, and design flexibility count for as much as peak interconnect performance. That happens to be the market where Google, Meta, and everyone else building custom silicon is spending its energy, and it’s growing fast.

The next 18 months settle much of this, through Intel’s late-2026 equipment deliveries, AP Memory’s SiCap ramp against that 10,000-unit target, SK Hynix’s HBM validation results, and whatever Meta does or doesn’t say about MTIA. The Google relationship, once it’s running at volume, won’t just evaporate. The thread I’d actually watch is MediaTek’s survival in the middle of it, because Google’s flirtation with going direct to TSMC is the one move that could gut Intel’s revenue while the packaging itself is still winning on the merits.