Five hundred thousand. That’s the on-off current ratio China’s Institute of Microelectronics, part of the Chinese Academy of Sciences, is reporting for a new gate-all-around transistor built entirely on deep ultraviolet lithography, with no EUV involved, according to a DIGITIMES report that started circulating September 17. I’ve been staring at that number for a day now, and the more I dig into what it actually measures, the less it tells me about whether China just cracked the 3nm problem it can’t buy its way out of.

Start with what gate-all-around buys you that FinFET doesn’t. A FinFET controls its channel from three sides; GAA wraps the gate completely around a stacked sheet or wire channel, which suppresses the short-channel leakage that gets worse every time you shrink gate length. Stack enough nanosheets and tune their width, and you can grow the effective channel area without growing the transistor’s footprint on the wafer. None of that requires EUV specifically. It’s a structural trick, not a lithography trick, which is exactly why it’s attractive to a research institute working under a lithography gap the Dutch government has no plans to close, and to a foundry, SMIC, that ASML now can’t even service under the MATCH Act’s ban on maintaining the DUV tools already sitting in Shanghai.

So the on-off ratio: it’s on-current divided by off-current, a measure of how cleanly a transistor tells the difference between on and off when it switches. A ratio of 500,000 is genuinely good. It’s also just a ratio, which means it says nothing on its own about how fast the thing switches, what voltage it needs, or how much current it drives per unit of width. You can hit a huge ratio with a big on-current and a tiny off-current, or with a small on-current paired with an even smaller off-current, and those describe very different transistors for very different reasons.

Here’s where it gets annoying. A 137.8 MTr/mm² density figure, pitched as roughly matching TSMC’s 5nm-class density, has been circulating since the DIGITIMES report broke, and Wccftech ran with it in its headline. That number isn’t from the Institute of Microelectronics. It traces back to someone on X doing back-of-envelope math from assumed standard-cell dimensions, the kind of estimate that ignores everything that actually determines real density: cell types, blank areas, power routing, timing margins. Treating it as an official figure is exactly the kind of laundering that makes claims like this impossible to evaluate a year later, once nobody remembers where the number came from.

The institute isn’t starting from zero on this, either. Its 2023 FishboneFET and TreeFET work, published in IEEE Electron Device Letters, tackled this exact problem of growing channel area without growing footprint, and a 2025 follow-up used a low-temperature ozone treatment before gate formation that cut interface state density by two orders of magnitude and pushed subthreshold swing to 60.3 millivolts per decade, close to the theoretical limit. I can’t confirm the September device shares that lineage; the report doesn’t say, but this isn’t coming out of nowhere.

What I keep coming back to is the gap between a transistor and a chip. Building one excellent GAA device on DUV tells you almost nothing about whether you can wire a billion of them together. After the front-end process forms the device, you still have to connect source, drain, and gate through a middle layer, then route signal and power through several metal layers above that. Shrink the contacts and resistance climbs. Shrink the wiring and parasitic capacitance climbs with it. Repeat enough exposure and alignment steps and eventually a via misaligns with the layer underneath, and now there’s a dead circuit sitting next to a working one for reasons nobody can point to cleanly. When Samsung announced 3nm GAA mass production back in 2022, the numbers it gave, up to 45% lower power at the same performance, up to 23% better performance at the same power, up to 16% smaller area- described power, performance, and area as one package, backed by a mass-production design ecosystem. A single transistor with a good on-off ratio is not that package, and the DIGITIMES report never actually says whether “3nm-class” refers to the transistor itself, a design rule, or a logic density nobody has measured yet.

I don’t think this claim is nothing. It lands three years into the EUV wall I’ve been tracking on the SMIC side, and a domestic institute running peer-reviewed GAA research on tooling it isn’t embargoed from is a real hedge against a wall that isn’t coming down anytime soon, especially for a foundry that’s still posting the kind of profit growth that funds this sort of long research bet. I just don’t think the “China matches TSMC 5nm” story that’s been floating around for two days, and a random X user’s density estimate getting laundered into a chip headline before anyone checked where it came from, is more interesting to me than the transistor itself.

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