TSMC put 3nm into volume this month on a transistor it has been shipping since 2015. The fin is that old, and N3 is the last time TSMC will use it. After this the structure changes for everyone, and the only argument left is when. Samsung already answered, jumping to gate-all-around at its own 3nm back in June. TSMC looked at the identical wall, judged Samsung too early, and chose to squeeze one final node out of the fin while it gets the hard transistor ready for 2nm.
N3B yields so badly that TSMC is already standing up a second, looser version of the node for everyone who is not Apple. The density gain over 5nm is real, just thinner than the slides promised. Stack on more EUV layers and a wafer price that prices out everyone below the very top of the market, and N3 reads less like a shrink than a toll booth. The first variant is in volume now. N3E, the relaxed one, lands next year, and that is what most of the industry will actually design on. The node is real. The version most companies can afford to ship on is still a year away.
Samsung got to the new transistor first. Gate-all-around nanosheets at 3nm, six months ahead of TSMC. Real engineering, and almost nobody bought it, because being first to a transistor you cannot yield in volume wins you a headline and not much else. TSMC keeps refusing that trade. It ships what customers are already lining up for and leaves the exotic process in the lab until the yield is real, and that has beaten Samsung’s flashier instinct every time the two have diverged. N3 is the same call one more time. Another node of fin, and the hard transistor waits for 2nm.
A chatbot went viral last month and bent the entire industry’s attention toward large AI models, almost overnight. The chips those models train on are giant datacenter accelerators, and they want the exact silicon TSMC is now charging a fortune for at N3. For a decade the leading edge ran on phones, on Apple and Qualcomm volume that funded every new generation like clockwork. That assumption is wobbling. I cannot tell yet whether this AI surge is a real structural shift or a bubble that pops by summer, and anyone who tells you they know is guessing. What I can see is N3 getting pulled at by two completely different customers at once, the handset and the server rack, for the first time ever.
For fifty years a smaller transistor meant a cheaper transistor. At N3 that stops. The cost per transistor, for a lot of designs, comes out flat against N5 or higher, so the shrink buys you speed and power and saves you nothing, and only the companies that can eat that bill bother. The list is short now. A few phone makers, a couple of datacenter buyers, and almost everyone else frozen out at the door. The leading edge has finished becoming a luxury good, and there is exactly one store that stocks it.
Intel says it will pass TSMC by the middle of the decade. A new transistor, plus a backside power-delivery trick it claims leapfrogs the whole Taiwan roadmap. And a side business renting that same capacity to other chip designers, a bet TSMC has never once had to make. Intel has also missed nearly every node target it set in the last ten years, so the promise is worth nothing until silicon ships and someone independent measures it. And still, TSMC’s own customers are quietly hoping Intel means it this time. A foundry with no competitor charges N3 prices and never stops, and the only thing that breaks that grip is a second company that can build at the edge. Intel is the only candidate standing. Thin thread to hang a market on.
The fin transistor that carried the industry from 16nm to here is finished after N3. At the same moment the cost curve that justified shrinking for half a century has gone flat, and the customers who funded the climb are turning from phone makers into AI shops that were not a budget line a month ago. TSMC walks into all of it as the only company that can build at the leading edge, which sounds like the safest seat in technology and mostly is. Yield climbs with time, and the relaxed variant handles the cost. The transistor change waiting at 2nm is hard but scheduled, and schedules are the kind of problem engineers know how to grind down. Geography is the one that has no engineering answer. Every leading-edge fab TSMC owns sits on a single island a much larger neighbor claims as its own, and no wafer price ever quoted can buy a second one somewhere safer. That is the risk that actually ends the company, and it is the only line on the whole page that 3nm changed nothing about.