TSMC is ramping 65nm into volume this year, a step behind Intel on the calendar and comfortably ahead of everyone who shares its business model. The gap to Intel used to be the headline. It is turning into the least interesting thing about this node. The sharper question 65nm forces is who can still afford to put a design on the leading edge at all, because that list gets shorter every generation.
65nm is a roughly 2x density step over the 90nm process TSMC ramped in 2004, and on paper that is the same bargain the industry has run since the 1970s: shrink the geometry, double the transistors, drop the cost per gate. The paper is starting to lie. The lithography on the critical layers is still 193nm argon-fluoride, the same wavelength that printed 90nm, pushed further with optical proximity correction and phase-shift masks and every other resolution trick the fabs own. Strained silicon stretches the channel to move electrons faster. Low-k dielectrics between the copper wires fight the RC delay that scaling keeps making worse. None of that is geometric scaling. It is a stack of expensive patches keeping Moore’s number alive while the physics underneath it quietly stops cooperating.
At 65nm the transistor leaks current even when it is switched off, through a gate oxide now only a handful of atoms thick and a channel too short to fully close. Nobody prints that number on the slide. Static power, the power a chip burns doing nothing, has stopped being a rounding error against switching power and become a constraint that can decide whether a part ships. The industry already conceded the first round of this last year, when it quit chasing clock frequency and started gluing cores together instead. The megahertz race is over, and 65nm is the first node designed for a world that already knows it.
The fix everyone is chasing is to rebuild the gate out of new materials, a high-k dielectric to choke off the tunneling and a metal gate to go with it. It is the most-discussed line in every process roadmap right now and it is in volume nowhere. Whoever ships it first at the next node buys a real leakage advantage, and every foundry in the business knows exactly what that is worth.
TSMC does not design chips. That is the entire point of it. It rents the hardest manufacturing problem on the planet by the wafer to companies that own no fab and never want to. NVIDIA, the graphics outfit whose old rival ATI is being swallowed by AMD as we speak, builds nothing itself. Qualcomm, Broadcom, Xilinx, Marvell, same story. Their silicon lives or dies on a yield number generated in Hsinchu that they do not control and mostly never see. The bet under the whole arrangement is that splitting design from fabrication beats keeping them under one roof, the way Intel does it, the way the IBM-led alliance of Samsung and Chartered is trying to.
That bet gets stronger every time a node gets more expensive to build, and they all do now. A leading-edge mask set runs into the millions before a single good wafer comes out. The R&D to qualify a process and the capex to fill a fab with the tools to run it climb every generation, faster than the density gains pay them back. Fewer companies can justify a leading-edge tape-out at 65nm than could at 90nm, and fewer still will clear the bar at 45nm. The leading edge is becoming a club with a cover charge that goes up every node. TSMC is not a member. TSMC owns the door.
The next step is 45nm, and that is where 193nm finally meets a wall it cannot trick its way through. The answer the whole industry is leaning on is immersion, running the exposure through a thin layer of purified water to bend the optics into one more shrink, the same bet ASML just rode past Nikon to make. It works on a research tool. Doing it in volume, at a defect rate a foundry customer will sign off on, is the problem TSMC has to crack next, because dry 193nm does not reach 45nm and nothing else is ready to.
TSMC already books around half of all foundry revenue on earth, and UMC, the other big Taiwanese house, sits second without cracking twenty percent, slipping further back on the leading-edge layers every year. Everyone else has worked out they cannot outspend TSMC alone, so they are pooling: IBM, Chartered, and Samsung have lashed their 65nm and 45nm process development into one shared platform, three R&D budgets aimed at a single recipe to match the scale TSMC funds by itself. It is a sensible move and a quiet admission of how the math now runs. Further back, SMIC is still finding its feet at 90nm and burning nearly as much energy in court with TSMC over process secrets as it does in the cleanroom. Matching TSMC on the leading edge has stopped being something any single second-tier player pulls off on its own balance sheet.
Perso, the density number is the part of this I care about least. 65nm doubles the transistors and the press release writes itself. The thing worth watching is the list of names that can still afford to walk through TSMC’s door, because every node since 90nm has made it shorter and nothing about 45nm reverses that. The fabless model was supposed to democratize silicon, let anyone with a good design rent a great fab. It is quietly doing the opposite. The fabs keep getting fewer and so do the designs that can pay for them, and the company sitting in the middle of that squeeze, charging all of them rent, is the one in Taiwan that never puts its name on a finished chip.