CATEGORY_INDEX // 66 ENTRIES

Foundry

Infographic: gate-all-around nanosheet transistor made via DUV lithography (no EUV), with 500,000:1 on-off ratio reported by CAS Institute of Microelectronics; disputes viral 137.8 MTr/mm2 density claim as unverified back-of-envelope math, not China's actual data
CHIPS & AI · 09/26/2026

China Claims a 3nm-Class Transistor Without EUV

China's Institute of Microelectronics reports a significant 500,000 on-off current ratio for a new gate-all-around transistor using deep ultraviolet lithography. However, this measure alone…

4 MIN
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Infographic: TSMC raising 2nm capacity from 90,000 to 110,000 wafers/month by mid-2027, and CoWoS packaging from 130,000 to 260,000 wafers/month by 2028, backed by $60-64B 2024 capex. Meanwhile chip stocks slide the same morning after Dario Amodei's AI caution: NVDA -4.71%, TSM -3.28%, ASML -3.65%, AMD -4.19%, as markets price in an AI slowdown despite strong foundry capacity signals
CHIPS & AI · 09/17/2026

TSMC Just Raised Its 2nm Capacity Guidance

TSMC plans to increase its 2nm capacity from 90,000 to 110,000 wafers monthly by mid-2027 and aims for significant growth in its 3nm and…

4 MIN
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