Twelve compute chiplets on TSMC’s N5 node, ringed around a single I/O die on the older, cheaper N6. That isn’t a roadmap slide, it’s the AMD EPYC sitting in datacenters right now, and it’s the clearest snapshot of where every serious AI chip is going: away from the monolithic slab of silicon that defined the last forty years.
I keep coming back to this because it rhymes with something I wrote a few weeks ago. When I argued that Qualcomm’s $4 billion grab for Modular was really a bet against CUDA, the point was that the software layer is coming unglued: break the CUDA lock and the moat drains out the bottom. Turns out the hardware is doing the same thing, one tile at a time, and almost nobody is connecting the two trends even though they point in exactly the same direction.
The reason is physics, not fashion. Moore’s Law slowed, the reticle limit on a single die is a hard wall, and yields on one enormous slab of silicon fall apart the moment you push past it. Chiplets route around all of that. The biggest win is that you stop paying bleeding-edge prices for circuits that never needed them: AMD puts its compute tiles on TSMC’s leading node and parks the I/O die on a mature, cheap N6 process, because I/O analog circuits were never going to scale to advanced nodes anyway. You also get to mix and match tiles instead of respinning a monolithic monster every cycle, and that last part is the one quietly rewiring who holds power in this industry.
The boring milestone that actually matters
None of that meant much while every chiplet had to come from the same vendor. What changed is UCIe, the Universal Chiplet Interconnect Express, and the membership list is the whole story: more than 120 companies now, with Intel and AMD and TSMC and Samsung sitting at the same table as ARM, Meta, and Google. Early in 2026, UCIe 3.0 landed its first live cross-vendor interoperability demo, and that is the unsexy headline that counts. A spec is just a PDF until two different companies’ silicon actually talks to each other on a shared package. That just happened.
The numbers underneath are almost absurd. UCIe pushes up to 64 GT/s, bandwidth density runs to roughly 1.3 TB/s per shoreline millimeter, and the energy cost of shoving a bit between tiles has dropped to about 0.01 picojoules. Moving data across the package is now so close to free, energy-wise, that the old argument for cramming everything onto one die has basically evaporated. The patent record tells the same story from a different angle: filings in this space went from 152 in 2017 to over 1,000 by 2024, and the bulk of that landed in the last two years as AI demand made the math undeniable.
The chokepoint just moved
Here’s the part that complicates the happy story. If the die stops being the bottleneck, packaging becomes it, and packaging is brutally concentrated. TSMC’s CoWoS line is the single most fought-over commodity in tech, climbing from around 80,000 wafers a month at the end of 2025 toward a target near 130,000 by late this year, and it still isn’t enough. I’ve written before about how CoWoS capacity, not GPU design, is what actually gates NVIDIA’s shipments, and chiplets make that dependency worse, not better, because more of the value now lives in the assembly step.
TSMC is racing ahead on the next tiers too: SoIC stacking logic and memory in three dimensions, and a panel-level approach called CoPoS that swaps the round wafer for a 310 by 310 mm square carrier and could multiply chips per panel, with equipment validation expected around Q3 2026 and real volume not until 2028. Intel is the only credible counterweight, leaning on EMIB and Foveros and an IDM 2.0 strategy that has gone openly fab-agnostic, outsourcing some tiles to TSMC while doing final assembly in-house. That would have been heresy five years ago. Now it’s just survival. I’m not going to wade into the glass-substrate and panel-level packaging weeds here, because that’s a rabbit hole that deserves its own post, but it’s where a lot of the 2027 fighting will happen.
Why the hyperscalers love this
Follow the incentive and the strategic payload is obvious. Microsoft, Google, and Amazon are all designing their own AI silicon now, Maia and the TPU line and Trainium, and chiplets are what make that viable without becoming a full-stack chip company overnight. They drop their proprietary accelerator logic onto a tile, pair it with off-the-shelf I/O and memory dies and a standard interconnect, and hand the package to a foundry. The result is a path to sovereignty, a way to tailor hardware to Gemini or Azure workloads while cutting their dependence on any single vendor. This is the same unbundling logic I traced through Qualcomm’s full-stack edge play, just aimed at the datacenter instead of the robot.
Even NVIDIA is hedging. Its Rubin platform still keeps the proprietary NVLink-C2C fabric for the internal superchip stitching, but NVIDIA is also a loud UCIe promoter, because it needs its hardware to slot into the modular datacenters its own customers are now building. When the company whose GPU monopoly I keep writing about starts backing the open interconnect that lets rivals mix and match around it, you know the wind shifted.
The proof that the barrier to entry actually dropped showed up at ISSCC in early March, when the Korean startup Rebellions presented the Rebel100, a quad-chiplet AI accelerator built entirely around UCIe-Advanced links, each tile carrying its own neural cores and shared memory. A startup shipping a four-chiplet accelerator is exactly the kind of thing that was impossible when you needed a monolithic megadie and a billion-dollar tapeout to play.
So who actually wins
The honest answer is messier than the modular-utopia pitch. HBM is the constraint that won’t quit: HBM4 and 16-high stacks are rolling out, demand keeps outrunning supply, and the thermal and yield risk on those towers is real. Hybrid bonding is becoming mandatory just to keep up, and that pushes even more leverage toward the handful of players who can do it. So the moat doesn’t disappear when the die stops being monolithic. It relocates. It moves to whoever writes the interconnect standard and, far more importantly, whoever owns the packaging line. Right now that is still overwhelmingly TSMC, which means “modular” and “democratized” are not the same word, no matter how often they get used together.
One open question I can’t resolve yet sits down in mobile. Phones have stayed stubbornly monolithic for power and area reasons, and whether chiplets ever make sense inside a Snapdragon is the thing I’m actually watching, because that’s the moment this stops being a datacenter story and starts touching the device in your pocket.
Put the two halves together, the software coming unglued from CUDA and the hardware coming apart into tiles, and you get the same conclusion from both directions: the integrated, one-vendor-does-everything model that made NVIDIA untouchable is being unbundled in slow motion. I think the unbundling wins in the end. I’m just not convinced it sets anyone free, because the company holding the new chokepoint is the same one that held the old one.