Meta signed. That is the line from Qualcomm’s June 24 Investor Day that I did not have when I argued for weeks that the phone was never the point and the destination was always the rack, and it reframes everything announced alongside it. Qualcomm rolled out a full data center brand called Dragonfly and stacked three new classes of silicon under it. It also signed a multi-generation supply agreement with Meta, the same morning. The bet I had been reading off spec sheets and acquisition filings is now an org chart with a customer logo on it.
Dragonfly is the brand, and it slots in beside Snapdragon for the consumer side and Dragonwing for the industrial edge I pulled apart in the IQ10 robot brain. Three names, one architecture lineage running from a wearable up to a rack. That edge-to-cloud spread is the exact structural advantage I kept circling in the AI200 piece, and Qualcomm has now turned it into the literal product portfolio. Underneath the dragonfly-as-efficient-flier marketing sit the three product lines that matter, and the CPU is the one that landed the headline customer.
Meta’s logo landed on a CPU, not an accelerator, which is the twist I did not see coming. I spent three posts on the AI200 and AI250 inference accelerators and on the Modular buy that really targets CUDA. The Dragonfly C1000 is none of that. It is a 250-plus-core server CPU built on custom Oryon cores clocked past 5 GHz, with PCIe Gen 7 and CXL, that Qualcomm says delivers more than twice the performance per watt of competing server chips. Meta is adding it to its next-generation server fleet, and Zuckerberg attached his name to the announcement. That is the customer “not already quoted in a Qualcomm press release,” I said I was waiting for at the end of the AI200 piece. It showed up on the one product line I was not tracking.
Second half of 2028. That is when the C1000 enters production, and Meta’s fleet starts running on it, and the broader CPU line maintains the same 2028 availability. So the strongest validation of the entire data center thesis is a commitment to silicon more than two years out, unveiled at an Investor Day that the stock had already climbed into. A name like Meta takes the demand question off the table. The execution question between a June 2026 slide and a humming 2028 rack is wide open, and Qualcomm has never shipped a data center CPU before, so there is no track record to lean on yet.
133 terabytes per second per card. That is what Qualcomm now puts on the AI250 under a new architecture it calls High Bandwidth Compute, and it is the number I was waiting for. In the AI200 post, I flagged that LPDDR’s weak spot is bandwidth and that the AI250 would try to close the gap with near-memory compute, where Qualcomm had claimed more than 10x the effective bandwidth, and I said I would believe it when an independent data center published a figure. The official figure is now 18x over the AI200 from HBC Gen 1, which 3D-stacks compute onto memory, comfortably past the 10x I was hedging on. A third accelerator, the AI300 with HBC Gen 2, takes that to 54x.
The roadmap reads as an annual cadence now, each generation a memory-bandwidth story rather than a raw-FLOPS one:
| Accelerator | Memory | Effective bandwidth vs AI200 | Sampling / availability |
|---|---|---|---|
| AI200 | LPDDR5X, 768 GB per card | baseline | 2026 |
| AI250 | HBC Gen 1 | 18x (133 TB/s per card) | sampling mid-2027 |
| AI300 | HBC Gen 2 | 54x | sampling 2028 |
Six times the bandwidth per watt of HBM, and two hundred times the capacity per watt of SRAM. Those are the two efficiency claims Qualcomm is aiming straight at NVIDIA, both normalized by Qualcomm against competitor specs Qualcomm picked. If they hold, HBC is the first answer to the HBM cost and power wall without requiring more HBM, which is the road NVIDIA and AMD are both still driving down. The load-bearing word is if. HBC Gen 1 samples in mid-2027, the AI300 with Gen 2 in 2028, and nobody outside Qualcomm has run a model on any of it. The AI200, the part closest to market, still has not surfaced in a third-party benchmark I can find.
UALink and ESUN carry the AI300’s scale-up. Both are open standards, and that choice matters more than the headline projection of four to eight times the performance per watt of today’s GPU architectures. UALink is the scale-up standard the rest of the industry built because it was tired of paying the NVLink tax, and Qualcomm planting Dragonfly on open interconnect is the same anti-lock-in reflex that drove the Modular buy. The whole platform is disaggregated and multi-vendor by design, which is the only shape that lets a newcomer slide into racks NVIDIA already owns.
Modular never came up today, and that silence is the most telling part. Qualcomm now owns every hardware layer the pitch requires. Everything in the release is hardware: tokens per watt and total cost of ownership. The compiler layer I argued was the real move against CUDA stayed backstage. That tracks with how these announcements sequence, because silicon has a roadmap and a logo to show Wall Street, while the software that lets a developer target that silicon without a rewrite is the unglamorous part that decides whether the hardware sells at all. It is the same value migration off the transistors and onto the integration layer I traced when the chips started coming apart into chiplets, and the same wall I ran into on the Snapdragon 8 Elite Gen 5’s NPU, one level up. Qualcomm showed the body today, leaving the nervous system offstage.
NVIDIA still owns training and CUDA, and it still sells the GB-class racks that frontier labs pay anything for, with a Grace-to-Vera CPU line on Arm beside them. AMD brings HBM accelerators and ROCm, and sits at the UALink table too. The hyperscalers run their own TPUs and Trainium, and with Meta now taking a Qualcomm CPU, the willingness to mix vendors at the rack is real in a way it was not a few years ago. Qualcomm has no designs on the training crown. The fight it picked is inference at the lowest cost per token, on silicon no government can switch off. The buyer wants to read the power bill at quarter close. The catch sits inside its own lineup: the C1000 is Oryon, which is Arm, and where the RISC-V cores from the Ventana and Tenstorrent moves fit a portfolio whose flagship CPU is Arm is a question I am leaving open, because the answer is not in today’s release and I am not going to invent one.
So was I right? On the direction, clearly, and the Dragonfly brand and the Meta logo are a sharper confirmation than I expected this fast. On the timeline, I was early in a way that counts. This is a 2027 and 2028 roadmap, with a 2026 reveal, and Investor Day is precisely where a company debuts a future it needs the market to fund today. The thesis I have been stacking across these posts still rests on the one thing Qualcomm did not put on stage: whether developers ever target this silicon by default, and a Meta CPU order for 2028 does not settle it. I think this is the most credible data center roadmap anyone outside NVIDIA has shown. I also know the distance between a press release and a rack running in a Meta hall is where roadmaps like this slip, and 2028 is a long time to hold a position on a promise.