Over the long Memorial Day weekend in late May, while most of the American chip industry was at a barbecue, Huawei picked the moment to announce it had rewritten the rules of semiconductors. At the IEEE circuits symposium in Shanghai, board member He Tingbo stood up and unveiled the Tau Scaling Law, a proposed replacement for Moore’s Law, alongside an architecture called LogicFolding. The pitch was aimed squarely at the people who had sanctioned the company. Huawei would reach the transistor density of a 1.4nm chip by 2031 without ever touching the extreme-ultraviolet lithography machines the US has spent years keeping out of China. Stack and fold the logic instead of shrinking it, and route around the embargo with design cleverness. The timing of the announcement, dropped while Washington was off the clock, told you how pleased they were with themselves.
One month later, IBM walked in and set a better hand on the table. On June 25 it announced nanostack, a transistor architecture demonstrated at the 0.7nm node, which it called the world’s first sub-1-nanometer chip technology. Same core idea as Huawei, build the chip up instead of out, but a much more serious piece of engineering underneath it. And that is the part that quietly deflates the Chinese claim, which I will get to, because it is the actual story here and almost nobody framed it that way.
What “0.7nm” is really hiding
Ignore the number. A node label stopped describing a physical dimension years ago. 0.7nm, or 7 angstroms, is a marketing marker for a generation of technology, not the size of anything on the die. The transistors are not 7 angstroms wide. What matters is how IBM got the density that earns the label, and that is where nanostack is interesting.
For decades the recipe was flat. Lay transistors next to each other like single-story houses on a street, then shrink the houses so you fit more per block. That is Moore’s Law, and as Gordon Moore himself framed it, it was always an observation about economics dressed up as a physical trend, not a law of nature. The industry has been scraping the bottom of it for a while now. Push features much smaller and you start fighting quantum tunneling, leakage current that never fully switches off, manufacturing tolerances measured in atoms, and fabrication costs that go vertical even when the transistors do not.
So IBM went up. Nanostack vertically stacks nanosheet transistors and, in the move that makes it clever, staggers them. The top layer is offset from the bottom one rather than sitting directly on it. That offset is not cosmetic. It means the front and the back of each transistor can be contacted independently, so signal lines and power lines can reach the devices without fighting each other for the same routing space. The layers are joined by 3D sequential integration, bonding wafers together with an ultra-thin dielectric, and because the layers are built in sequence rather than patterned together, each one can use a different material tuned for its job. The bottom transistor and the top transistor no longer have to be compromises of the same recipe.
If you have been following the transistor roadmap, you already know the word for where this sits. After FinFET, which the industry has run since around 2012, came gate-all-around nanosheet, which is finally shipping in 2025 and 2026. The agreed next step after that is CFET, the complementary FET, which stacks the n-type and p-type transistors on top of each other instead of side by side. Nanostack is IBM’s route into the CFET era, a staggered, sequential take on it. IBM invented gate-all-around nanosheet back in 2021 and called it a 2nm-class design, so this is the same lab extending its own roadmap into the next dimension. That lineage matters when you weigh the credibility.
The numbers, and why I half-trust them
IBM says nanostack delivers up to 50% more performance, or up to 70% better energy efficiency, against its own 2nm node from 2021. It packs close to 100 billion transistors onto a piece of silicon the size of a fingernail, roughly 666 million transistors per square millimeter, about double the density of that 2nm chip. A separate paper at this year’s VLSI Symposium showed a 40% improvement in SRAM density using the staggered approach, which matters more than it sounds because on-chip memory has been the stubborn part of scaling and AI accelerators are starving for it.
Here is the caveat I cannot ignore. Every one of those figures is projected or simulated against IBM’s own previous node, not measured on a product you can buy. What IBM did validate is the hard physics, and that is the part I respect: ultra-thin dielectric bonding in a real CMOS integration flow, dual-channel engineering, and a functional CMOS inverter that switches the way the model says it should. That is the difference between a press release and a result. A working inverter built with staggered, bonded nanosheets is not slideware. It is proof the thing can be physically built and will compute. But proof of physics is a long way from a yielding wafer, and IBM is candid about the distance.
Now the Huawei comparison, because this is the whole point
Both companies are betting the future is vertical. They agree on the diagnosis completely. Where they split is on the quality of the answer, and on one inconvenient piece of physics that Huawei’s framing tries to walk past.
Huawei’s LogicFolding fuses two separate wafers together, folding whole sheets of logic on top of each other. It is a coarser cut at the same idea: stack at the wafer level, compress the distance a signal has to travel, and let the Tau Scaling Law reframe the goal from “smaller transistors” to “shorter signal time.” IBM’s nanostack does its stacking down at the individual transistor, with the stagger that lets each device be contacted and tuned on its own. One is folding floors of a building together. The other is redesigning the apartments. Both are 3D, but they are not the same resolution of 3D.
Then there is validation. IBM showed working test structures and a node. Huawei showed a scaling law, an architecture concept, and a suite of design tools, including a 3D verification platform called Argus, with no third-party confirmation of any of it. He Tingbo claimed Huawei has already mass-produced 381 chips on these principles over six years, which is the kind of number that sounds precise and proves nothing without someone outside the company measuring it. Analysts who were asked about the original announcement were polite and unconvinced.
And the timelines tell the real story. Huawei is targeting density equivalent to 1.4nm by 2031. TSMC is targeting actual 1.4nm, its A14 node, for mass production in 2028. So the headline pitch, stripped of the Moore’s Law theatrics, is “give us three extra years and a completely different road and we will arrive at the same place TSMC reaches in 2028.” That is not a leapfrog. That is running the same race three years back with the announcer turned up.
The thing nobody put at the top of the story
Here is what makes IBM’s move land as a quiet rebuttal rather than just a parallel flex. Huawei’s entire argument is that going 3D lets it escape the sanctions box because you no longer need the bleeding-edge lithography to keep winning. IBM just demonstrated that the most advanced players, the ones with full access to that lithography, are going 3D too, further along, validated in silicon, and they still have the EUV underneath.
You cannot fold your way out of the need for good lithography. The layers you are stacking still have to be patterned, and patterning fine features still runs through extreme-ultraviolet machines that only ASML makes and that China cannot buy. SMIC, Huawei’s foundry and the linchpin of China’s whole domestic chip effort, tops out at a 7nm-class process using older deep-ultraviolet tools and a lot of multipatterning gymnastics. IBM developed nanostack at its Albany research site, which is about to install an ASML High-NA EUV system, working alongside Lam Research, Tokyo Electron and SCREEN to build the manufacturing recipe, with Rapidus in Japan, one of the few lines running a High-NA tool today, as its production licensee. Going vertical does not delete the EUV bottleneck. It just moves where the bottleneck bites. Huawei’s 3D story is real engineering, but as a sanctions escape hatch it leaks, because the sanctioned-out incumbents are doing the same 3D move with tools Huawei still does not have. Sanctions, not nanosheets, remain the story.
Why mass production is the part that humbles everyone
This is where I cool down on all of it, IBM included, because a staggered sequential CFET is monstrously hard to manufacture. You are bonding wafers with alignment tolerances that have to land within a fraction of a nanometer, then building one transistor layer on top of another without the heat from the second step cooking the first. Thermal budget is the quiet killer here. Every high-temperature stage you run to make the top device degrades the one already sitting underneath it, and the whole appeal of sequential integration is that you built the bottom one first. Then you have to get heat back out of a three-dimensional stack that has far less surface area to shed it through than a flat chip does, inspect for defects buried inside layers you can no longer see from above, work out repair strategies, and do all of it at a yield that does not bankrupt you.
And there is a tooling gap that bites both companies. The EDA software needed to design logic in three dimensions at the transistor level does not really exist yet. IBM said as much, that those tools “need to arrive.” Which is a little ironic, because Huawei’s whole pitch leaned heavily on its own 3D design tools as the differentiator. The honest read is that nobody has the full software stack to design these chips at scale, and that is as real a barrier as the physics. You can validate an inverter in a lab without it. You cannot tape out a 100-billion-transistor processor without it.
The part of IBM’s story I keep chewing on
IBM does not manufacture chips at volume. It sold that business to GlobalFoundries back in 2015. What it does is invent architectures, prove the physics, and license the know-how to the foundries and to partners like Rapidus, while its own Telum and Power processors get built on someone else’s leading-edge line. Samsung, in fact, fabs IBM’s own Power and Z chips.
Sit with that for a second, because it complicates the victory lap. IBM invented gate-all-around nanosheet and then watched Samsung get it to production first in 2022, TSMC bring it to N2, and Intel ship its RibbonFET version, while the wafer economics of the thing IBM pioneered flowed to the companies that built the fabs around it. IBM monetized it through patents and its research alliance, which is a fine business, but it is not the same business as selling the silicon. Nanostack could run the exact same script. Brilliant first, validated first, and then commercialized and sold by everyone else. Jay Gambetta, who runs IBM Research, said the company is not even disclosing yet how it will commercialize nanostack, and that its near-term focus is helping partners scale today’s 2nm. Production is roughly five years out. Five years is a long time in this industry, and it is enough time for the foundries to fold the good ideas into their own CFET roadmaps, leaving IBM holding the citation.
I am leaving the export-policy angle alone here, whether nanostack changes how Washington thinks about the controls, because that is a whole separate post and frankly above my pay grade. The engineering is what I came for.
Where this leaves the scoreboard
On the merits, it is not close. IBM showed a validated, transistor-level 3D architecture with a working circuit, a coherent path into the CFET era, and the entire ASML-and-foundry ecosystem standing behind it. Huawei showed a scaling framework, a wafer-folding concept, an impressive-sounding chip count nobody can check, and a 2031 target that lands three years behind TSMC’s real one. If you are scoring the physics, IBM went one better and it is not particularly debatable.
But I would not hand IBM the trophy either, because both of these are research milestones years from a fab, every IBM number is measured against IBM’s own past chip rather than a shipping product, and the company’s own history is a long lesson in inventing the future and letting other people sell it. The thing that decides who wins is not whose nanosheets stagger more elegantly. It is who stands on the right side of the ASML line, and Huawei still does not. IBM wins the physics, Huawei wins the propaganda cycle it engineered over a holiday weekend, and a Dutch company that makes lithography machines quietly owns the choke point that determines what either of them can ever ship. Ask me which of those three I would bet on, and it is not the one with the press release.