TSMC’s A14 node just started pilot production at Fab 20 in Baoshan and Fab 25 in Central Taiwan Science Park, according to Taiwan’s UDN, and the detail that actually matters isn’t the date; it’s the tense. TSMC is running ahead of its own internal schedule. Risk production is still slated for 2027 and high-volume manufacturing for 2028, but a company that guards its own timelines this closely only volunteers “ahead of schedule” when it thinks it can afford to pull the date forward later, not push it back.

I’ve been tracking A14 all year because TSMC told a room full of engineers back in August that this node would skip ASML’s High-NA EUV tool entirely, standard EUV and clever multi-patterning instead of the $380 million machine, purely to keep mask count down. That decision is still holding. A14 promises up to 15% higher speed at the same power as N2, or up to 30% lower power at the same clock, plus a 20% jump in logic density, and none of it needs the tool TSMC spent September quietly signing up to co-develop for whatever node comes after this one. Skip the expensive machine for the node you’re actually shipping. Help write the standard for the one you’ll need eventually. That’s not indecision, that’s knowing which fights to pick and when.

What I actually want to talk about is Intel, because Intel’s side of this got strange this week in a way that doesn’t add up on paper. Naga Chandrasekaran, Intel Foundry’s chief technology and operations officer, told the investment bank KeyBanc that 14A is expected to land “within 5%” of TSMC’s A14. On its face, that’s a modest, reasonable thing to say about the node that’s supposed to be Intel’s actual comeback bet, the one I called out back in January as needing a customer more than it needs a spec sheet. The problem is that Intel’s own published numbers don’t get anywhere near “within 5%.” Intel says 14A should deliver 15 to 20% higher performance at the same power as 18A, or 25 to 35% lower power at matched clocks. TSMC says A14 delivers 10 to 15% over N2 on that same axis. Run those ranges against real shipping silicon: Intel’s Core Ultra X9 388H hitting 5.10GHz on 18A against the fastest N2 part on the market, and the math puts 14A somewhere between 2% and 16% ahead of A14 depending on which end of each range you pick. Not one of those scenarios lands at “within 5%” unless Intel undershoots its own floor while TSMC hits its ceiling at the same time.

So either Chandrasekaran is being careful in front of an investment bank, which is a normal thing to do after your last few node promises didn’t all land on schedule, or “within 5%” is doing quiet work to lower expectations ahead of a node that still doesn’t have the marquee customer 18A eventually found once Panther Lake actually shipped. I lean toward the first explanation, mostly because the quote reached press through a third party’s account of an investor call rather than an Intel press release, and that’s exactly the kind of thing that gets flattened and re-quoted until it sounds more definitive than it was. But the timing bothers me anyway. TSMC picks this week to say its most advanced node is running early. Intel picks the same week to publicly set the bar for its answering node lower than its own spec sheet supports.

None of this tells you who actually wins 14A versus A14, and I don’t think anyone outside either fab knows yet, including whoever was on that call with KeyBanc. What it does tell you is that TSMC is currently the only party in this comparison acting like it has nothing to prove.

Sources