7nm has been in volume production since 2018. The equipment is long depreciated, the yields dialed in. Anyone who picked it over 3nm did so partly to dodge the cost volatility of the bleeding edge. That node, the boring stable one, just got a price hike, and by every account customers did not see it coming. That’s the detail that made me stop and re-read the report, because it breaks an assumption the whole industry had quietly filed under settled.
The rest was telegraphed. TSMC’s top management told its business development and sales teams to find mechanisms for raising prices across every node in the portfolio. Sub-5nm (2nm, 3nm, 4nm, 5nm) gets flagged 3 to 5% annual increases starting January 2026, compounding into double digits over successive years. The broader portfolio sits at 5 to 10%. Analysts tracking TSMC’s margin targets had penciled those in already. Nobody penciled in 7nm, and the assumption it broke runs deep: that mature nodes had reached a kind of pricing equilibrium where the only direction left was down.
A 3nm wafer runs roughly $20,000, and 2nm is expected to carry a 10 to 20% premium on top of that, lower than the 50% floated in earlier reports but still a real step up. Build that wafer in Arizona instead of Taiwan and you add another 5 to 20%, with some reports citing up to 30% for 4nm specifically. Lisa Su confirmed the Arizona differential out loud on an earnings call. Fabless CEOs do not discuss foundry pricing in public, and she did, which tells you how normalized this has already become.
None of it started with TSMC. SK Hynix and Samsung pushed through steep DRAM and HBM increases on the back of AI infrastructure demand, and TSMC’s management cited those moves directly as cover for its own. Call it “if they can, we can,” running up and down the supply chain at once. The memory makers got there first, and TSMC simply read the room. That simultaneity is the trap: there is no component category to substitute into. Memory is up and logic is up, with advanced packaging and substrates climbing right alongside them. The entire bill of materials for an AI accelerator or a high-end SoC inflates in parallel, and the customer eats all of it.
Underneath sits AI demand that stopped being cyclical and became load-bearing. HPC and AI workloads hit 61% of TSMC’s total revenue as of Q1 2026, and advanced nodes (7nm and below) make up 74% of wafer revenue. Sub-5nm capacity is fully subscribed. To feed NVIDIA, Apple, and AMD, TSMC has been pulling workforce and equipment off mature nodes and pointing them at the leading edge, which quietly starves 7nm of the capacity that would otherwise leave it in comfortable oversupply. The scarcity there is partly manufactured by TSMC’s own resource shuffle. The customer feels it the same either way.
Geopolitics bolts on a cost layer that is structural and non-negotiable. TSMC’s committed Arizona investment has reached $165 billion, the largest single foreign direct investment in U.S. history. Kumamoto and Dresden carry their own premiums. These fabs exist because governments demanded them, and their higher labor costs and thinner local supply chains, plus the regulatory overhead, have to land on somebody. CFO Wendell Huang, in a BBC interview on June 9, 2026, said inflation is pushing costs up and declined to rule out more hikes, while ruling out sudden “fourfold, fivefold” jumps. CC Wei told the June 2026 shareholder meeting he would “like” to raise prices. The official line is that pricing is “strategic, not opportunistic,” which is true in the narrow sense that the increases are planned and graduated. It changes nothing for the customer.
EUV is the cost nobody can engineer around. ASML holds a complete monopoly on extreme ultraviolet lithography, and its High-NA tools, required for 2nm and beyond, run $150 million to $380 million each. No second supplier, and no credible timeline for one. Every new node needs more EUV exposure steps than the last, so lithography’s per-wafer contribution climbs with every transition. TSMC cannot negotiate this down. It flows straight into the wafer price as a fixed input.
That ratchet finally broke the oldest promise in the business. For roughly sixty years, every new node delivered more transistors per dollar, and the cost curve bent down over time. It held through 130nm, 90nm, 65nm, 45nm, 28nm, 16nm, 10nm, started straining at 7nm, and at 2nm it inverted: cost-per-transistor at 2nm is higher than at 3nm, which was higher than at 5nm. This is not a yield-ramp wrinkle that smooths out as the node matures. It is what happens when you push lithography against physics, and the industry has no prior experience with a node that gets more expensive per transistor the longer it lives.
The margin math makes the motive plain. TSMC targets a gross margin of at least 53%. Overseas fabs initially shave 2 to 3 points off that, and the current hike cycle is projected to add back roughly 2. The hikes are, in large part, a mechanism for clawing back the dilution from a geographic expansion customers never asked for and cannot opt out of. They are subsidizing U.S. and European industrial policy through their wafer orders, line by line.
Who actually bleeds depends on where you sit. NVIDIA, Apple, and AMD have the margins and the leverage to absorb a near-term increase or pass it downstream slowly. Apple, the expected first volume customer for 2nm, runs hardware gross margins above 45%, which buys room. NVIDIA’s data center margins make a 5 to 10% wafer increase painful, not existential. Costs reach consumers eventually, in next iPhones, AI PCs, and high-end GPUs, but the transmission lag gives these companies time to manage it.
The mid-tier fabless shops, automotive chip designers, and industrial IoT SoC makers who built their cost models on 7nm staying flat have no such buffer. Thinner margins and less negotiating leverage, with no way to redesign onto a different node on short notice. A 5 to 10% bump at 7nm lands directly as margin compression or a price increase, and for anyone selling into automotive Tier 1 or industrial automation, neither is a clean choice. Automotive has its own trap on top of that: ADAS and EV compute platforms have been migrating onto 7nm and 5nm to keep up with modern driver assistance, so these buyers are deepening their advanced-node dependence right as the hike arrives. They were already bruised by the 2021 to 2023 shortage. And automotive programs run four to seven years, so a cost increase baked into a platform today sets program economics for most of a decade.
The ripple keeps going past wafers. TSMC’s hikes validate and reinforce the Samsung and SK Hynix memory increases, the OSAT and substrate suppliers are fighting their own cost pressures, and advanced packaging capacity is its own bottleneck now, with ASML, Applied Materials, and Lam Research facing zero competitive reason to drop tool prices. For cloud and AI services the path is slower but just as directional: pricier chips raise the capex to build compute clusters, which raises the cost basis for cloud compute, which eventually seeps into SaaS and AI API pricing. Quarters to years, not weeks, but the pressure only points one way.
So is this a cyclical spike or a permanent reset? Structurally it reads as a reset, and the most decisive reason is competitive: there is no escape hatch. Samsung Foundry is the only theoretical alternative at advanced nodes and not a functional one, its 3nm GAA yield troubles well documented, and customer confidence built over years of tape-outs and design-rule familiarity and supply reliability does not transfer on demand. Intel Foundry under Lip-Bu Tan is running a real turnaround but sits years away from credible leading-edge volume, and the EUV ceiling that boxes in everyone outside the TSMC-ASML axis is not lifting on anyone’s convenient schedule. TSMC holds about 70.2% of all foundry revenue and an even larger slice of advanced-node capacity. It reads the board as well as anyone, and its pricing reflects exactly that.
Everything else reinforces it. The Arizona, Kumamoto, and Dresden fabs are hundreds of billions in committed infrastructure with multi-decade lifespans; their premiums will narrow as local supply chains thicken but the gap to Taiwan costs persists. TSMC’s labor costs keep climbing, with employee profit sharing up roughly 30% year-over-year for three straight years as TSMC, Samsung, SK Hynix, and the overseas operations all bid for the same engineers. Demand offers no relief either, with AI accelerators, autonomous compute, industrial robotics, AI PCs, and next-gen phones all converging on sub-5nm at once.
And the node-complexity curve has no reverse gear. Every generation past 2nm wants more EUV passes and more advanced packaging than the one before. The cost-per-transistor line, having inverted, is not going to flip back. The one idea I would bet hard against is that 7nm ever drifts back to the price customers had quietly assumed was permanent. That floor is gone, and nobody is rebuilding it.