TSMC’s 2nm capacity is set to jump from 90,000 wafers a month to 110,000 by mid-next year, and that’s the smaller of the two numbers worth watching. Taiwan’s Economic Daily News, citing supply chain sources rather than TSMC’s own investor relations desk, reports the foundry has, for the first time, laid out its 2027 targets: 2nm capacity climbing 22 percent and 3nm growing more than 16 percent between the end of this year and mid-2027. The 3nm number goes from roughly 180,000 wafers a month to 210,000, which sounds modest until you remember 3nm is about to pass 5nm as TSMC’s single largest revenue line.

I keep coming back to the CoWoS number, though, because it’s the one that actually explains the rest. TSMC is reportedly aiming to double its CoWoS advanced packaging capacity, the stuff that turns a Blackwell or Rubin die into a shippable GPU, from around 130,000 wafers a month at the end of this year to 260,000 by the end of 2028. I’ve written before about how CoWoS outsourcing to OSATs was Nvidia’s fault long before it was TSMC’s problem, and this is the sequel nobody asked for: instead of just handing packaging overflow to Amkor and the rest, TSMC is building its own way out, expanding AP7 in Zhunan and standing up new advanced packaging lines in Arizona so finished dies don’t have to ship back across the Pacific before they’re usable. Capex guidance moved with it, up from roughly $50 billion to $60 to 64 billion for the year, with 70 to 80 percent of that going toward the advanced nodes and packaging specifically.

None of this reads like hedging. Development on A14, A13, and A12, the nodes that come after this year’s A16, is already underway with ASML, and TSMC is reportedly moving toward 12-inch photomasks as part of that transition. This is a company that looked at 2026’s AI demand and decided it wasn’t a bubble worth planning around cautiously, so it wrote a multi-year capacity commitment instead.

Which makes the timing almost funny. The same morning this guidance surfaced, chip stocks were sliding on a completely different story: Dario Amodei’s public call to slow down frontier AI development, and the pile-on from Sam Altman and Elon Musk that followed it over the weekend. SK Hynix and Samsung took real hits in Asia, ASML followed in Europe. I’m not relitigating the Amodei essay here; that’s its own post and a good one. But it’s worth sitting with the contradiction for a second: the market spent Monday morning pricing in the possibility that AI development needs to slow down, on the same day the company that actually builds the chips underneath all of it quietly told its suppliers to build a lot more, a lot faster, through 2028. Markets react to essays. Foundries react to backlogs. I know which one I’d trust for a read on what Nvidia and AMD are actually ordering eighteen months out.

A real question remains whether Intel’s EMIB-T packaging becomes a meaningful pressure valve here. Analysts cited alongside the same supply chain reports put Intel’s CoWoS-equivalent capacity climbing from 15,000 to 20,000 wafers a month in 2027 up to 40,000 to 45,000 in 2028, enough to matter specifically for Google and Amazon’s custom silicon. I’m skeptical Intel Foundry executes on that timeline given everything else on its plate, but that’s a different article.

What I trust less is any framing that makes TSMC look generous. Sony just bet $4.7 billion that Kumamoto rebuilds fast enough to keep image sensor production on schedule, and Apple’s M6 shipped as the company’s first 2 nanometer part in the cheap Mac Mini, not the flagship, because that’s where TSMC had room. Every customer has learned the same lesson this year: capacity gets allocated to whoever pre-commits hardest, and TSMC’s real moat was never just the process node, it’s the orchestration of who gets which wafer when. Doubling CoWoS by 2028 doesn’t fix that scramble. It just raises the ceiling while keeping the queue exactly as brutal as it’s been all year.

Sources