TSMC is reportedly expanding CoWoS outsourcing to its OSAT partners, and the number that explains why is ugly: Nvidia alone has reportedly locked up somewhere between 800,000 and 850,000 wafers of TSMC’s total CoWoS capacity for 2026, more than half of everything the foundry can produce this year. Add in the custom-ASIC crowd building their own AI silicon and you get a foundry that still can’t close the gap between what customers want and what its packaging lines can physically deliver, even after years of being warned this was coming.

The specific change, per sourcing out of Korea’s ETNews, is that TSMC is handing a much bigger share of CoW, the step where the chip gets attached to the interposer, to OSAT houses including ASE. That’s new. TSMC has always kept CoW in-house and outsourced the other half of the process, WoS, bonding the interposer to the substrate, to ASE, Amkor and SPIL under license. CoW was the part it held onto, the piece of CoWoS that made it hard for a customer to shop the packaging step around even if they found cheaper wafers somewhere else. Cracking that open is a small, real concession from a company that has spent years treating advanced packaging as the moat that mattered as much as the node itself.

The capacity math tells you how stretched things actually are. TSMC’s monthly CoWoS output was running around 70,000 wafers in 2025 and is projected to climb to 130,000 to 140,000 wafers by the end of this year, nearly doubling in twelve months. Even at that pace, the reporting puts the CoWoS supply-demand gap at roughly 20% for 2026. Doubling capacity in a year and still landing a fifth short is the actual story here, not the outsourcing headline.

What I find more interesting is that TSMC doesn’t look like it’s leading this. Back in June, Mirror Daily reported that ASE and SPIL had already started steering a chunk of their 2026 advanced packaging capex toward building their own CoW lines, with backing from customers like AMD, specifically to route around TSMC’s bottleneck: fab the wafer at TSMC, then ship it straight to ASE or SPIL for the full CoWoS build, cutting TSMC’s own packaging line out of part of the sequence entirely. If that’s accurate, the arrangement TSMC is reportedly formalizing now isn’t a strategy so much as TSMC catching up to a workaround its own customers had already started building around it.

This slots right into the packaging bottleneck story I’ve been tracking all year. I wrote about the CoWoS bottleneck hiding behind Blackwell B300 shipments back in June, and about Intel trying to turn the same bottleneck into an opening for EMIB a few weeks later. The pattern holds: every advanced-packaging chokepoint in this industry traces back to the same root cause, which is that AI chip demand outran the physical capacity to package chips years before anyone outran the capacity to fab them. The chiplet turn I covered in June was supposed to be the industry’s answer to exactly this problem, and it’s still not enough on its own.

OSAT firms are apparently already placing equipment orders on the strength of this, with purchase-order discussions underway with South Korean suppliers for dicing gear (to cut wafers and interposers) and bonding equipment (to join them). That’s the detail I actually trust here. Anonymous sourcing to a Korean trade outlet is one thing. Capital equipment orders are a different kind of confirmation, because nobody spends real money on dicing tools for a rumor.

Whether this dents TSMC’s pricing leverage is the part I can’t answer yet. I’ve written before about TSMC raising prices in 2026 with no real floor in sight, largely because nobody else can package chips at the volume or yield TSMC can. If ASE and SPIL genuinely build out independent CoW capability instead of just executing TSMC’s overflow, that pricing leverage erodes a little every quarter it continues. I don’t think this is the quarter that happens. But the equipment orders are already going out, and that’s usually how these things start.

Sources