Coming into 2026, hybrid bonding was the technology that would define HBM4, the moment memory stacking finally broke past the thermal and density walls that bump-and-underfill assembly kept slamming into. Then in July 2026, ZDNet Korea reported that Samsung and SK hynix are both rethinking whether to bother with it at HBM4 at all. The trigger is a quiet move from JEDEC: a proposed loosening of the ceiling on how tall an HBM stack is allowed to be.
That one parameter carries more weight than it looks, so start with what hybrid bonding solves and why the height limit made it urgent.
Conventional HBM stacking runs on thermal compression with non-conductive film, TC-NCF. Every DRAM die connects to the one below through microscale copper bumps, and the gap between dies gets packed with a non-conductive underfill that holds the joint together mechanically. It works. It carried HBM from the original two-layer parts through HBM2E and HBM3E. But it drags two penalties along that get worse the taller you stack.
The first is thickness. Each die-to-die interface in a TC-NCF stack eats a fixed slice of vertical budget: bump height, underfill layer, and the die itself. A 12-high stack of DRAM plus a base logic die squeezes into 775 µm total package height at HBM3E, which is exactly the JEDEC ceiling for that generation. Try to cram 16 layers into the same envelope and the geometry stops cooperating. The per-layer budget shrinks until thinning the dies can’t make up for the underfill and bump thickness piling up across 16 interfaces.
The second penalty is heat, and it’s about materials. Underfill is a polymer, and polymers conduct heat badly. Every die-to-die interface sits behind a layer that actively fights heat trying to flow from the upper dies down into the substrate. HBM4 aims for roughly double the bandwidth of HBM3E, which means more switching and more heat, and all those stacked insulating layers turn into a real ceiling on sustained performance.
Hybrid bonding kills both problems at the root. Forget bumps and underfill; it forms direct copper-to-copper bonds between the metal pads on facing die surfaces. Surface activation, precise alignment, an anneal, and the copper diffuses across the interface until the two pads become one continuous conductor. No bump height to account for, no polymer between dies. You get a thinner stack per layer and a metal heat path at every interface instead of an insulating one, plus finer pad pitch than bumps can ever reach, which is what lets you pack in more terminals. SK hynix showed a 12-stack HBM part built with hybrid bonding in April 2026, so the process clearly works at real layer counts. Everyone expected it to make its commercial debut with HBM4.
Then JEDEC started moving the goalposts. HBM physical specs live in the JESD235 standard family, and one of the numbers that family pins down is maximum total stack height, the envelope an HBM package has to fit inside to stay compatible with the interposers and package designs the GPU and accelerator vendors build around. For HBM3E that’s 775 µm. ZDNet Korea’s March 2026 reporting said JEDEC was seriously weighing a bump to somewhere between 825 and 900 µm for HBM4. The July follow-up pushed the picture further out: HBM5 might get loosened again, from 900 µm up toward 1,000 µm. These are numbers from industry sources, not published standard text, and JEDEC hasn’t put out a press release nailing them down, but both reports point the same way.
Raise the ceiling by 50 to 125 µm and the whole calculus flips. Manufacturers can hit their 12-layer targets on plain TC-NCF without needing the per-layer thickness savings hybrid bonding was there to deliver. The geometric forcing function just evaporates. A 12-layer TC-NCF stack that would have blown past 775 µm now sits comfortably inside 825 or 900. Hybrid bonding’s thickness win was the main near-term reason to swallow its yield and process headaches, and that reason gets a lot weaker overnight.
The thermal case doesn’t vanish with a taller envelope, because underfill insulates no matter how much vertical room you give it. But the industry’s answer, per the same reporting, is to reach for external heat dissipation devices rather than rebuild the bonding process. That’s not a small distinction. Hybrid bonding pulls the thermal resistance out at the source by deleting the insulating material entirely, while an external heat sink treats the symptom, dragging heat off the outside of the package after the fact. Whether those two approaches land in the same place on sustained thermal performance, at the power densities HBM4 is going to run, is an open question. The reporting carries no measured numbers, and structurally the two aren’t doing the same job.
Both Samsung and SK hynix look likely to push hybrid bonding out of HBM4 and into HBM4E, with the technology going mandatory no later than HBM5E. And the reason it becomes mandatory then has nothing to do with height. The number of I/O connections per die keeps climbing, and eventually the pitch you need is finer than bumps can physically hit. At that point hybrid bonding isn’t a choice anymore, whatever the thickness ceiling happens to say.
The 16-layer stack conversations that used to ride alongside HBM4E have gone dormant, per ZDNet, which hints that even HBM4E might stay a 12-layer product and take still more pressure off adopting hybrid bonding before HBM5E. Layer count is the cleanest place hybrid bonding’s per-layer savings turn into something TC-NCF simply cannot match inside a fixed envelope, and if nobody’s chasing 16 layers, that advantage has nowhere to show up.
NVIDIA sits underneath all of this. As the dominant buyer of high-bandwidth memory for AI accelerators, its near-term demand signals move memory makers’ product plans more than anything else does. When NVIDIA isn’t pushing hard for high-layer-count HBM in the immediate roadmap, the commercial reason to eat hybrid bonding’s process risk ahead of schedule mostly disappears. JEDEC sets the physical envelope, but the customers set the performance targets that decide whether anyone actually needs to push against it. When your biggest customer says 12-layer HBM4 on conventional bonding is good enough for now, the case for pioneering a brand-new bonding process at production scale falls apart, even while the long-term technical argument for it stays intact.
None of this is a cancellation. It’s a slip. Hybrid bonding is going into HBM production; the HBM5E floor on I/O density makes that a near-lock. But shoving it from HBM4 to HBM4E or HBM5 eats into the learning runway before HBM5E, the generation where it stops being optional. And it’s a far nastier process than TC-NCF: tighter surface prep, smaller alignment tolerances, a steeper yield curve once you’re at real volume. A manufacturer who brings it in at HBM4E gets one generation of production experience before HBM5E forces the issue. Whoever waits for HBM5 gets less. The technology itself isn’t in doubt, since SK hynix’s April demo proves it runs. The doubt is whether yield and throughput at scale take longer to tame than the compressed schedule leaves room for.
There’s a real irony waiting at the end of this. If the thickness relaxation lands in published form, a standards body will have loosened a constraint and, in doing so, postponed the exact innovation that constraint was driving. Nobody designed the 775 µm ceiling to force hybrid bonding adoption, but that’s precisely what it was doing. Lifting it buys everyone breathing room today and leaves the long-term necessity untouched. The runway is the part that should keep memory makers up at night: the window to build real process maturity is now narrower than the moment it’s meant to prepare for.