Five years ago, a process engineer would have told you that fabbing a 7nm-class chip without EUV was economically irrational, maybe physically implausible. SMIC did it anyway. That deserves a serious look, and a serious look means separating what teardowns have confirmed from the numbers bouncing around Chinese semiconductor forums and Western tech blogs that ran well ahead of any evidence.
One claim making the rounds says SMIC’s third-generation N+3 node hits smaller metal pitch than Intel 18A, or beats TSMC N6 on transistor density. As of mid-2025 there is no verified primary source behind either statement. Nobody has published a peer-reviewed teardown of an N+3 chip. The figures trace back to speculative Weibo analysis and secondary reporting citing other secondary reporting, and writing them down as fact would be misinformation. The documented reality is already a better story than the fabrication.
TechInsights pulled apart the Huawei Mate 60 Pro after its August 2023 release, the most rigorous public examination of SMIC’s advanced work anyone has done, and confirmed the Kirin 9000s inside ran on a 7nm-class SMIC process. Metal pitch measured in the ~40nm range, transistor density estimated around 100 million per square millimeter. That puts SMIC N+1 at or just below TSMC’s original 2018 N7 node, which lands near 91 MTr/mm² and did it without EUV too. N+2 and the claimed N+3 are incremental steps on that base. N+3 could plausibly nudge into TSMC N7+ territory around 108 MTr/mm². Reaching N6’s ~171 MTr/mm² without EUV, though, is not something the consensus of process engineers thinks multi-patterning refinement can deliver, full stop.
For pure reference, here are the verified or consensus-range figures:
| Node | Foundry | EUV? | Density (MTr/mm²) | HVM Entry |
|---|---|---|---|---|
| N7 | TSMC | No | ~91 | 2018 |
| N6 | TSMC | Partial | ~171 | 2021 |
| N5 | TSMC | Yes | ~173 | 2020 |
| N3E | TSMC | Yes | ~290 | 2023 |
| N+1 | SMIC | No | ~100 (est.) | 2022 |
| N+3 | SMIC | No | Unknown | 2024–25? |
| Intel 18A | Intel | Yes | ~238 (claimed) | 2025 risk prod. |
| SF3 | Samsung | Yes | ~250 (claimed) | 2025 |
Intel 18A isn’t even playing the same game. It pairs RibbonFET gate-all-around transistors with PowerVia backside power delivery, and SMIC has demonstrated neither. Lining up metal pitch between 18A and N+3 as if they were peer process generations confuses geometry with architecture, which is most of what makes the viral comparison bogus.
The achievement and its limits both live in the mechanism. EUV at 13.5nm wavelength prints features that 193nm immersion DUV cannot resolve in a single shot. TSMC, Samsung, and Intel pattern their most critical layers in one or two EUV exposures with tolerable overlay error. SMIC has zero of these machines. ASML has been blocked from shipping EUV into China since 2019, and the Dutch tightened the screws again in January 2024, restricting even some advanced DUV scanners including the NXT:2000i and newer immersion tools.
So SMIC leans hard on multi-patterning, Self-Aligned Double and Quadruple Patterning (SADP and SAQP). If you can’t print a 20nm half-pitch in one exposure, print a 40nm pattern, then use spacer deposition and selective etch to split it into two 20nm features. SAQP takes that to four features per original exposure. The execution is brutal, because every split adds deposition, etch, and alignment steps. A single EUV layer TSMC does in one pass can cost SMIC three to five DUV steps, dragging along 20 to 30% more mask layers than TSMC N7 for comparable geometry, by industry estimates.
Every one of those extra steps introduces alignment uncertainty, and that compounding overlay error is the real enemy. TSMC N7 overlay budgets are already tight; push to SMIC’s multi-patterning depth and the accumulated error eats into margins that were thin to start with. Yield, not geometry, is the constraint that actually bites. SemiAnalysis and TechInsights both modeled SMIC’s 7nm-class yield and landed in the 40 to 60% range, against TSMC N7’s mature 80%-plus. That is a capacity problem as much as a cost one: to ship the same count of good dies, SMIC needs roughly 1.5 to 1.7 times the wafer starts. With a tool base they cannot freely expand, that math caps total output cold. The Mate 60 Pro’s supply crunch through late 2023 and early 2024 was exactly this ceiling made commercially visible. Wafer cost runs 2 to 3 times TSMC’s equivalent, so SMIC’s advanced nodes only pencil out for customers with no alternative: Huawei HiSilicon, state-backed AI accelerator programs, and similar captive demand.
The density of N+3 matters less than where DUV multi-patterning simply runs out of road, and the process-engineering literature puts that wall somewhere around 5nm-class geometry. Overlay error stacks multiplicatively with each step, and SAQP is already near the practical edge of what immersion DUV yields acceptably. A hypothetical octuple-patterning SAOP would demand overlay control no current DUV scanner can hit. TSMC N5 at ~173 MTr/mm² and N3E at ~290 MTr/mm² aren’t reachable by refining multi-patterning; they need EUV, and N3E needs a lot of it.
That wall is a harder limit on China’s AI chip ambitions than any software or architecture problem. Huawei’s Ascend 910C, reportedly built on SMIC processes, competes in the H100-era bracket for inference. But the next wave of large-scale training infrastructure, the systems meant to push past current frontier scale, wants the transistor density and interconnect bandwidth that only N3-class and eventually N2-class silicon provides. SMIC cannot get there on DUV. The distance between "good enough for Huawei phones and domestic AI chips today" and "competitive for frontier accelerators in 2027" is not something DUV-bound process refinement closes.
Can China invent around EUV entirely? Three technical paths exist, and none is a near-term fix. Domestic EUV is the most direct. SMEE, Shanghai Micro Electronics Equipment, is China’s main lithography toolmaker, and its production capability sits around 28nm-class DUV, not even the immersion lithography SMIC uses for 7nm. Its roadmap toward immersion and eventually EUV is real but aspirational, with most outside analysts putting Chinese domestic EUV five to ten years behind ASML’s current generation. ASML isn’t waiting either. High-NA EUV, already shipping to Intel and TSMC for sub-2nm work, is another full generation of separation.
Directed Self-Assembly offers a different angle. DSA uses block copolymer chemistry to self-organize into regular patterns at pitches finer than lithography alone can manage, and it can hand DUV sub-lithographic patterning for certain layer types. Chinese academic and industrial research into it is active and promising as a way to stretch DUV further. The catch is integration: DSA’s difficulties have kept it out of high-volume leading-edge production even at TSMC and Samsung.
Nanoimprint lithography is the wildcard I’d watch closest. Canon’s NIL tools escape the export controls that pin ASML’s scanners, and Canon has been selling them. NIL can hit very fine pitches, with Canon demonstrating sub-10nm half-pitch in research, but throughput and defect density have historically kept it out of high-volume logic. Whether it can be pushed into a viable production alternative for specific critical layers is an open research question, and Chinese money is flowing toward finding out. Realistically, none of these delivers inside a two-to-three year window, so SMIC’s likely near-term path is grinding more out of the DUV envelope, better process control and resist chemistry, tighter overlay on SADP and SAQP, while the domestic equipment ecosystem slowly matures underneath it.
The equipment story has a human one riding alongside it that gets far less airtime. Liang Mong Song, SMIC’s co-CEO and the architect of its advanced node program, came out of TSMC and Samsung, and his hands-on knowledge of leading-edge process development is a big part of why SMIC reached 7nm production at all. His contract reportedly expired or is expiring in 2024, which makes him a real variable in whatever comes next. Process engineering at this level doesn’t live in documentation. It lives in the judgment of engineers who’ve run these flows through thousands of iterations. Everyone fixates on the equipment controls, but who knows how to do this, and which fab they walk into every morning, matters just as much.
SMIC’s broader team has clearly absorbed serious process knowledge across the N+1 and N+2 cycles. The distance from TSMC’s N3E to SMIC’s N+3 isn’t a knowledge gap you close by reading papers, though. It’s a gap in equipment capability, in yield learning banked over millions of wafer starts, and in the feedback loop between tool and process that you only get from running EUV at scale, which SMIC has never done.
Strip away the hype and what SMIC proved is real: 7nm-class production without EUV, not on a whiteboard but in commercial volume, enough to supply Huawei’s flagship line and feed domestic AI chips. The industry’s conventional wisdom underestimated that, and the Kirin 9000s landed with geopolitical force precisely because it wasn’t supposed to exist. But the distance between "possible" and "competitive" is wide, and it’s opening further. TSMC is shipping N3E and building N2. Intel 18A, ramp troubles and all, brings gate-all-around and backside power. Samsung SF3 is in the same neighborhood. SMIC N+3, whatever its final density, is competing against where TSMC stood in 2018 through 2021: fine for captive demand, nowhere near stable for frontier accelerators, HPC, and advanced mobile SoCs.
SMIC has bought China’s chip industry time and strategic breathing room. It has not bought a path to parity. The one thing worth doubting is the timeline everyone quietly assumes will bend in China’s favor: domestic EUV, DSA, NIL, or some stitched-together combination breaking the ceiling. That answer arrives on the scale of a decade, not a product cycle, and I wouldn’t bet the next two years on it.